Quiescent supply current (IDDQ) testing is a very effective test method for Complementary Metal-Oxide Semiconductor (CMOS) circuits. However, IDDQ vector verification and debugging may take considerable time and effort. Various problems have been encountered in such troubleshooting processes, so different tools and methodologies have been devised to address them. For pre-silicon IDDQ vector verification, a modular approach is adopted. IDDQ is estimated for each vector based on leakage libraries of cells, and cell constraints can be verified automatically. For post-silicon IDDQ vector issues, methods and analysis tools have been developed to identify the root causes. Scan cell and net value analysis will identify critical scan cells and nets, which will result in an IDDQ pattern either passing or failing, thus revealing the source of the extra leakage. These methodologies are proven to be successful for IDDQ vector debug and IDDQ diagnosis.
Additionally, IDDQ testing is a valuable test for low power CMOS circuits, since a small number of IDDQ vectors can achieve test effectiveness comparable to that of a much larger number of functional or other structural tests. In recent years, the technology trend of scaling down IC geometry by 40%-50% every two to three years, to achieve ever increasing performance and IC density, has resulted in a tremendous increase in the difficulty of IDDQ test development. According to the National Technology Roadmaps and other roadmap-related work, IC gate counts and cell leakage have been increasing. As a result, leakage current standard deviation for defect free chips has also been increasing, while defect-induced leakage has been decreasing. As a result, standard methodologies for identifying these defects such as Emission microscopy (EMMI) are either less efficient or not effective.
On the other hand, low power consumption is a key requirement for devices used in mobile applications, such as wireless communications, and this market is growing fast. Various methodologies have been devised or explored to reduce power consumption in these applications, including static leakage. Along with the physical geometries, power supply voltage is also scaling downward; this, along with various design and fabrication techniques, has helped offset the power consumption increase incurred by smaller feature size and the increasing number of transistors. Such devices are particularly suitable for IDDQ test; chips with around or below 1 mA of leakage can still be tested by conventional IDDQ. In fact, IDDQ provides an essential means for structurally testing for leakage defects that would have catastrophic affects on the sleep time of the end product. Also, to continue utilizing IDDQ and taking advantage of its efficiency for testing low leakage chips, many techniques have been adopted to prolong the lifetime of IDDQ, such as separate power regimes, delta IDDQ, current ratio, speed-leakage correlation, power supply gating (“footer” device), power supply partitioning, etc., such that IDDQ can be applied to detect defect-induced leakage on the order of 10 μA when total chip IDDQ is ˜10 mA. In IDDQ vector generation, verification, and debugging, various issues have been encountered, including custom cell design issues, implementation issues, constraint issues, etc. These issues also contribute to traditional debugging techniques being less effective. In addition, resolving these issues may take considerable time and effort.